To keep you informed I just copy and paste the last info from my private-diary:
Get a stable starting-point from scratch
Get the
latest bladerf software.
Nuand.com,
support, alle relevant … and end at https://github.com/Nuand/bladeRF
At right
of the page is download zip (yes, I know, I should clone, but don’t yet know
how, sorry…)
bladeRF-master
(3).zip is in my download-area.
Rename
old bladeRF-master to bladeRF-master03
Extract
to C:\bladeRF-master
May be
wise to get the latest firmware too.
The
latest image is pointed to by: http://www.nuand.com/fx3/latest.img
Download
latest.img and copy to C:\Program Files (x86)\bladeRF for loading with
bladerf-cli
To be
sure download FPGA-firmware from http://nuand.com/fpga/
choose V0.0.3 hostedx115.rbf
Rename
current hostedx115.rbf to hostedx115.rbf_01
Now copy
hostedx115.rbf to directory C:\Program Files (x86)\bladeRF
Now
connect bladerf-board using USB2-port, and flash latest.img, power remove/connect,
flash with hostedx115.rbf
Connect
power (I use external poweradaptor), connect to USB2
One
green LED D1 shows a nice constant green light.
Startup
bladerf-cli (I use windows by the way)
[WARNING] extract_field: Field checksum mismatch
[WARNING] Could not extract VCTCXO trim value
[WARNING] extract_field: Field checksum mismatch
[WARNING] Could not extract FPGA size
bladeRF> load fx3 latest.img
Flashing firmware from latest.img...
[INFO] Erasing 0x20000 bytes starting at address 0x00
[INFO] Erased sector at 0x00...
[INFO] Erased sector at 0x10000...
[INFO] Writing 0x20000 bytes starting at address 0x00
[INFO] Verifying 0x20000 bytes starting at address 0x00
Done. Cycle power on the device.
bladeRF>
Remove/reconnect
power
bladeRF> probe
Backend: libusb
Serial: b436de8c8212b9aeaaeba852246866e7
USB Bus: 2
USB Address: 6
bladeRF> version
bladeRF-cli version: 0.7.0-git
libbladeRF version: 0.9.0-git
[ERROR] status < 0: LIBUSB_ERROR_IO
Error: File or device I/O failure
bladeRF> exit
oeps,
error, disconnect/reconnect USB and restart bladeRF
[WARNING] extract_field: Field checksum mismatch
[WARNING] Could not extract VCTCXO trim value
[WARNING] extract_field: Field checksum mismatch
[WARNING] Could not extract FPGA size
bladeRF> load fpga hostedx115.rbf
Loading fpga from hostedx115.rbf...
Done.
bladeRF>
YEP!
LED2 blinks about 40 times in 10 seconds, LED1 is off and LED3 is on.
Now try to create hostedx115.rbf from scratch
From
this stable situation I am trying to create a new hostedx115.rbf with Quartus.
Little bit confusion about the LEDs
In the
file C:\bladeRF-master\hdl\fpga\platforms\bladerf\vhdl\ bladerf-hosted.vhd:
…
count := 100_000_00 ;
led(1) <= not led(1) ;
end if ;
end if ;
end process ;
led(2) <= tx_underflow_led ;
led(3)
<= rx_overflow_led ;
…
I would
expect led(1) to blink, not LED2
But, I
might presume that LED1 = led(1), LED2 = led(2) and LED3 = led(3) but is that
true?
The file
C:\bladeRF-master\hdl\fpga\platforms\bladerf\constraints\pins.tcl contains:
set_location_assignment
PIN_AA7 -to led[1]
set_location_assignment
PIN_AB7 -to led[2]
…
set_location_assignment
PIN_AB10 -to led[3]
Now to
the schematics to find:
Sheet 3
of 14 FPGA “LEFT” BANK
LED1 =
D11 AA7
LED2 =
D12 AB7
AB10 is
not connected on the schematic
On the bladeRF-board
I read
LED1 =
D12 (left)
LED2 =
D11 (middle)
LED3 =
D13 (right)
So, the
middle blinking LED must be led(1)
I guess
that the left LED must be led(2)
I’ll try
to change the blinking rate of led(1) and set led(2) to the on state ‘1’
But
firstly try to get a home-made hostedx115.rbf without any changes.
In Windows, you should be able
to open the Nios II Command Shell (look in your Start menu). You can then
navigate to the hdl/quartus directory and use the build_bladerf.sh script to
build your project.
You can open the resulting
project using the GUI in the work directory that gets created by the script.
Also note there is a README in
the HDL directory to help with compilation. We currently use Quartus II 13.1
for building. Please make sure you are up to date.
I keep an eye on your blog and
love what you're doing. Please keep it up! :)
Posted by Brian to SDR with
BladeRF at February 1, 2014 at 3:43 AM
Start,
Altera 13.1.0.162 Web Edition, NIOS II EDS 13.1.0.162, NIOS II 13.1 Command
Shell
------------------------------------------------
Altera Nios2 Command Shell [GCC 4]
Version 13.1, Build 162
------------------------------------------------
lonneke@lonneke-VAIO /cygdrive/c/altera/13.1
$ cd ..
lonneke@lonneke-VAIO /cygdrive/c/altera
$ dir
13.0sp1 13.1
lonneke@lonneke-VAIO /cygdrive/c/altera
$ cd ..
lonneke@lonneke-VAIO /cygdrive/c
$ dir
$Recycle.Bin END Music Quartus System\ Volume\ Information WirelessDiagLog.csv default_xdb
magazines version
BBHuur
Elektor POI RHDSetup.log Temp Xilinx eclipse pagefile.sys vmware
Backup\ docs\ iPad
Firefox PerfLogs SPLASH.000 Update _FS_SWRINFO fftrlog.txt prive
CampingWijzer
ISOimages Photo SPLASH.SYS Users altera hiberfil.sys splash.idx
Cypress
Intel Program\ Files Sdr Utrecht bladeRF-master homepage t
DesignSparkMech
Keil Program\ Files\
(x86) SiLabs VAIO\ Sample\ Contents bladeRF-master_01 java test.xml
Documentation
LinuxBoard ProgramData Softw\ Radio WinRadio bladeRF-master_02 javaprojects usb_driver
Documents\ and\ Settings
MSOCache Python27 SwSetup Windows bladeRF-master_03 lv.log user.js
lonneke@lonneke-VAIO /cygdrive/c
$ cd bladerf-master
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master
$ dir
CMakeLists.txt CONTRIBUTORS COPYING
README.md debian firmware_common fx3_firmware
hdl host legal
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master
$ cd hdl
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl
$ dir
README.md fpga quartus
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl
$ cd quartus
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl/quartus
$ dir
bladerf.tcl build.tcl build_bladerf.sh constraints
ip.ipx signaltap
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl/quartus
$ bash build_bladerf.sh -h
bladeRF FPGA build script
Usage: build_bladerf.sh -r <rev> -s <size>
Options:
-r <rev> FPGA revision
-s <size> FPGA size
-a <stp> SignalTap STP file
-h Show this text
Supported revisions:
hosted
headless
fsk_bridge
qpsk_tx
Supported sizes (kLE)
40
115
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl/quartus
$ bash build_bladerf.sh -r hosted -s 115
Press RETURN
or ENTER and go out with the dog for a short walk or go and listen to your partner
An
enormous amount of information appears in the window, after a few minutes the
last few lines read:
Info: Elapsed time: 00:00:14
Info: Total CPU time (on all
processors): 00:00:12
Info (23030): Evaluation of Tcl script ../build.tcl was successful
Info: Quartus II 32-bit Shell was successful. 0 errors, 89 warnings
Info: Peak virtual memory: 195
megabytes
Info: Processing ended: Sun
Feb 02 23:03:26 2014
Info: Elapsed time: 00:06:05
Info: Total CPU time (on all
processors): 00:00:02
/cygdrive/c/bladerf-master/hdl/quartus
##########################################################################
Done! Image copied to:
hostedx115.rbf
##########################################################################
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl/quartus
$
There it
is: hostedx115.rbf, I rename the file to hostedx115new.rbf and copy it to C:\Program
Files (x86)\bladeRF
The
proof of the pudding is in the eating:
Everything
is still fine on my bladerf-board, the LEDs are still blinking. SDR-RADIO.COM
SDR radio console works like a charm.
Now edit a file with the GUI of Quartus
You can open the resulting
project using the GUI in the work directory that gets created by the script.
Double-click
on C:\bladeRF-master\hdl\quartus\work\ bladerf.qpf
The GUI of Quartus opens!!!
I edit
the file ../../fpga/platforms/bladerf-hosted.vhd to read:
toggle_led1 : process(fx3_pclk)
variable count : natural range 0 to
100_000_000 := 100_000_000 ;
begin
if( rising_edge(fx3_pclk) ) then
count := count - 1 ;
if( count = 0 ) then
-- count := 100_000_00 ;
count :=
100_000_000 ; --
KdG 2-Feb-2014
led(1) <= not led(1) ;
end if ;
end if ;
end process ;
-- led(2) <= tx_underflow_led ;
led(2) = '1'; -- KdG 2-Feb-2014
led(3) <= rx_overflow_led ;
-- toggle_led2 : process(rx_clock)
-- variable count : natural range 0 to
38_400_00 := 38_400_00 ;
-- begin
-- if( rising_edge(rx_clock) ) then
-- count := count - 1 ;
-- if( count = 0 ) then
-- count := 38_400_00 ;
-- led(2) <= not led(2) ;
-- end if ;
-- end if ;
-- end process ;
Now try
the wholce circus again after having saved this file.
Just
click on save all and exit
What a
pity, at the end I get:
2014.02.02.23:31:37 Progress: Done reading input file
2014.02.02.23:31:38 Info: nios_system: Generating nios_system
"nios_system" for QUARTUS_SYNTH
2014.02.02.23:31:38 Info: pipeline_bridge_swap_transform: After
transform: 12 modules, 41 connections
2014.02.02.23:31:38 Info: No custom instruction connections, skipping
transform
2014.02.02.23:31:38 Info: merlin_initial_interconnect_transform: After
transform: 12 modules, 35 connections
2014.02.02.23:31:39 Info: merlin_translator_transform: After transform:
25 modules, 74 connections
2014.02.02.23:31:39 Info: merlin_domain_transform: After transform: 50
modules, 207 connections
2014.02.02.23:31:39 Info: merlin_router_transform: After transform: 63
modules, 246 connections
2014.02.02.23:31:39 Info: merlin_burst_transform: After transform: 64
modules, 249 connections
2014.02.02.23:31:40 Info: merlin_network_to_switch_transform: After
transform: 89 modules, 301 connections
2014.02.02.23:31:40 Info: merlin_width_transform: After transform: 91
modules, 307 connections
2014.02.02.23:31:40 Info: merlin_clock_and_reset_bridge_transform: After
transform: 93 modules, 399 connections
2014.02.02.23:31:41 Info: merlin_hierarchy_transform: After transform:
13 modules, 43 connections
2014.02.02.23:31:41 Info: merlin_mm_transform: After transform: 13
modules, 43 connections
2014.02.02.23:31:41 Info: merlin_interrupt_mapper_transform: After
transform: 14 modules, 46 connections
2014.02.02.23:31:41 Info: reset_adaptation_transform: After transform:
16 modules, 60 connections
2014.02.02.23:31:43 Warning: nios_system: "No matching role found
for uart_0:s1:dataavailable (dataavailable)"
2014.02.02.23:31:43 Warning: nios_system: "No matching role found
for uart_0:s1:readyfordata (readyfordata)"
2014.02.02.23:31:44 Error: Couldn't write
C:/bladeRF-master/hdl/fpga/ip/altera/nios_system/synthesis/nios_system.v
2014.02.02.23:31:44 Error: Generation stopped, 14 or more modules
remaining
2014.02.02.23:31:44 Info: nios_system: Done "nios_system" with
15 modules, 1 files, 53301 bytes
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl/quartus
$
Perhaps
I should do some cleaning?
From C:\bladeRF-master\hdl\quartus
delete directory work and try again
Same
problem:
------------------------------------------------
Altera Nios2 Command Shell [GCC 4]
Version 13.1, Build 162
------------------------------------------------
lonneke@lonneke-VAIO /cygdrive/c/altera/13.1
$ cd ..
lonneke@lonneke-VAIO /cygdrive/c/altera
$ cd ..
lonneke@lonneke-VAIO /cygdrive/c
$ cd bladerrf-master/hdl/quartus
bash: cd: bladerrf-master/hdl/quartus: No such file or directory
lonneke@lonneke-VAIO /cygdrive/c
$ cd bladerf-master/hdl/quartus
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl/quartus
$ dir
bladerf.tcl build.tcl build_bladerf.sh constraints
ip.ipx signaltap
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl/quartus
$ bash build_bladerf.sh -r hosted -s 115
## Non-Linux OS Detected (Windows?)
## Forcing QUARTUS_BINDIR to C:/altera/13.1/quartus/bin
##########################################################################
Generating NIOS II Qsys for
bladeRF ...
##########################################################################
2014.02.02.23:38:28 Progress: Loading nios_system/nios_system.qsys
2014.02.02.23:38:28 Progress: Reading input file
2014.02.02.23:38:28 Progress: Adding clk_0 [clock_source 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module clk_0
2014.02.02.23:38:29 Progress: Adding nios2_qsys_0 [altera_nios2_qsys
13.1]
2014.02.02.23:38:29 Progress: Parameterizing module nios2_qsys_0
2014.02.02.23:38:29 Progress: Adding spi_0 [altera_avalon_spi 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module spi_0
2014.02.02.23:38:29 Progress: Adding jtag_uart_0
[altera_avalon_jtag_uart 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module jtag_uart_0
2014.02.02.23:38:29 Progress: Adding onchip_memory2_0
[altera_avalon_onchip_memory2 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module onchip_memory2_0
2014.02.02.23:38:29 Progress: Adding timer_0 [altera_avalon_timer 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module timer_0
2014.02.02.23:38:29 Progress: Adding uart_0 [altera_avalon_uart 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module uart_0
2014.02.02.23:38:29 Progress: Adding spi_1 [altera_avalon_spi 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module spi_1
2014.02.02.23:38:29 Progress: Adding pio_0 [altera_avalon_pio 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module pio_0
2014.02.02.23:38:29 Progress: Adding iq_corr_rx_phase_gain
[altera_avalon_pio 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module
iq_corr_rx_phase_gain
2014.02.02.23:38:29 Progress: Adding iq_corr_tx_phase_gain
[altera_avalon_pio 13.1]
2014.02.02.23:38:29 Progress: Parameterizing module
iq_corr_tx_phase_gain
2014.02.02.23:38:29 Progress: Adding bladerf_oc_i2c_master_0
[bladerf_oc_i2c_master 1.0]
2014.02.02.23:38:30 Progress: Parameterizing module
bladerf_oc_i2c_master_0
2014.02.02.23:38:30 Progress: Building connections
2014.02.02.23:38:30 Progress: Parameterizing connections
2014.02.02.23:38:30 Progress: Validating
2014.02.02.23:38:30 Progress: Done reading input file
2014.02.02.23:38:34 Progress: Loading nios_system/nios_system.qsys
2014.02.02.23:38:34 Progress: Reading input file
2014.02.02.23:38:34 Progress: Adding clk_0 [clock_source 13.1]
2014.02.02.23:38:34 Progress: Parameterizing module clk_0
2014.02.02.23:38:34 Progress: Adding nios2_qsys_0 [altera_nios2_qsys
13.1]
2014.02.02.23:38:35 Progress: Parameterizing module nios2_qsys_0
2014.02.02.23:38:35 Progress: Adding spi_0 [altera_avalon_spi 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module spi_0
2014.02.02.23:38:35 Progress: Adding jtag_uart_0
[altera_avalon_jtag_uart 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module jtag_uart_0
2014.02.02.23:38:35 Progress: Adding onchip_memory2_0
[altera_avalon_onchip_memory2 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module onchip_memory2_0
2014.02.02.23:38:35 Progress: Adding timer_0 [altera_avalon_timer 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module timer_0
2014.02.02.23:38:35 Progress: Adding uart_0 [altera_avalon_uart 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module uart_0
2014.02.02.23:38:35 Progress: Adding spi_1 [altera_avalon_spi 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module spi_1
2014.02.02.23:38:35 Progress: Adding pio_0 [altera_avalon_pio 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module pio_0
2014.02.02.23:38:35 Progress: Adding iq_corr_rx_phase_gain
[altera_avalon_pio 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module
iq_corr_rx_phase_gain
2014.02.02.23:38:35 Progress: Adding iq_corr_tx_phase_gain
[altera_avalon_pio 13.1]
2014.02.02.23:38:35 Progress: Parameterizing module
iq_corr_tx_phase_gain
2014.02.02.23:38:35 Progress: Adding bladerf_oc_i2c_master_0
[bladerf_oc_i2c_master 1.0]
2014.02.02.23:38:35 Progress: Parameterizing module bladerf_oc_i2c_master_0
2014.02.02.23:38:35 Progress: Building connections
2014.02.02.23:38:35 Progress: Parameterizing connections
2014.02.02.23:38:35 Progress: Validating
2014.02.02.23:38:36 Progress: Done reading input file
2014.02.02.23:38:37 Info: nios_system: Generating nios_system
"nios_system" for QUARTUS_SYNTH
2014.02.02.23:38:37 Info: pipeline_bridge_swap_transform: After
transform: 12 modules, 41 connections
2014.02.02.23:38:37 Info: No custom instruction connections, skipping
transform
2014.02.02.23:38:37 Info: merlin_initial_interconnect_transform: After
transform: 12 modules, 35 connections
2014.02.02.23:38:38 Info: merlin_translator_transform: After transform:
25 modules, 74 connections
2014.02.02.23:38:38 Info: merlin_domain_transform: After transform: 50
modules, 207 connections
2014.02.02.23:38:38 Info: merlin_router_transform: After transform: 63
modules, 246 connections
2014.02.02.23:38:39 Info: merlin_burst_transform: After transform: 64
modules, 249 connections
2014.02.02.23:38:39 Info: merlin_network_to_switch_transform: After
transform: 89 modules, 301 connections
2014.02.02.23:38:39 Info: merlin_width_transform: After transform: 91
modules, 307 connections
2014.02.02.23:38:39 Info: merlin_clock_and_reset_bridge_transform: After
transform: 93 modules, 399 connections
2014.02.02.23:38:40 Info: merlin_hierarchy_transform: After transform:
13 modules, 43 connections
2014.02.02.23:38:40 Info: merlin_mm_transform: After transform: 13
modules, 43 connections
2014.02.02.23:38:40 Info: merlin_interrupt_mapper_transform: After
transform: 14 modules, 46 connections
2014.02.02.23:38:41 Info: reset_adaptation_transform: After transform:
16 modules, 60 connections
2014.02.02.23:38:42 Warning: nios_system: "No matching role found
for uart_0:s1:dataavailable (dataavailable)"
2014.02.02.23:38:42 Warning: nios_system: "No matching role found
for uart_0:s1:readyfordata (readyfordata)"
2014.02.02.23:38:43 Error: Couldn't write
C:/bladeRF-master/hdl/fpga/ip/altera/nios_system/synthesis/nios_system.v
2014.02.02.23:38:43 Error: Generation stopped, 14 or more modules
remaining
2014.02.02.23:38:43 Info: nios_system: Done "nios_system" with
15 modules, 1 files, 53301 bytes
lonneke@lonneke-VAIO /cygdrive/c/bladerf-master/hdl/quartus
$
Summary
For me all this was a giant step, perhaps a small step for Brian.
I created a stable start-point.
I managed to generate hostedx115.rbf using the NIOS shell (note the use of the command bash).
I managed to create a Quartus project and could use the GUI.
I managed to change bladerf-hosted.vhdl.
But I did not manage to compile again.
I should do some cleaning perhaps, or is there a command from the GUI?
Anyway, I had a great great evening this Sunday and now I am going for a walk with my dog and get some sleep.
.jpg)
He is not so smart to tell me what he wants by
waiting in the bathroom, I put him there for the picture...
